Digital Systems: From Logic Gates to Processors Week 6 Quiz Answer

Digital Systems: From Logic Gates to Processors Week 6 Quiz Answer

In this article i am gone to share Coursera Course: Digital Systems: From Logic Gates to Processors Week 6 Quiz Answer with you..

Graded Quiz 6 Answer

Question 1)

Design a 4-bit shift register that can (1) shift its information at right, (2) shift its information at left and (3) asynchronously initialize to state 0000 when RST=1.

The figure below shows the circuit inputs and outputs. (Use exactly these names. Respect upper and lower case):

clk: Input. Clock signal.

RST: Input. Reset signal.

N: Data input.

SL (Shift_Left): Input. When SL=1 (and SR=0), the information moves one position at left and IN inputs to the rightmost flip flop.

SR (Shift_Right): Input. When SR=1 (and SL=0), the information moves one position at right and IN inputs to the leftmost flip flop.

When SR=SL=0 or SR=SL=1 the information remains unchanged.

OUT: Output. It outputs the state of the rightmost flip flop.

Note 1: When using multiplexers from the library, set the “Include Enable?” field to NO to remove the "Enable" pin.

Note 2: To properly verify the circuit, VerilUOC_Desktop requires all inputs of the flip flops are connected to some value. In this case, "S" inputs must be connected to 0. Click in "Wiring" (left menu), select "Constant" and, in the Value property replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs.

Instructions to answer this question

1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.

2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.

3) In "Module" select "Graded Exercises" and click on exercise 6.1.

4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.

Answer: YVYZ

Question 2)

Design a 6-bit, shift-right register with D flip flops, and use it to implement a circuit that detects the sequence “110101” (the rightmost bit is the first arriving). Information shifts one position right when a positive edge of clk occurs.The circuit has the following inputs and outputs (use exactly these names for inputs and outputs. Respect upper and lower case):

clk: Input. Clock signal.

RST: Reset signal. When RST = 1 flip flops are reset to 0.

IN: Data entry. IN inputs to the leftmost flip flop at each rising edge of clk.

OUT: Output. Takes the value 1 when the last bit of sequence 110101 is detected (see example) and returns to 0 in the next clock cycle.

Note:To properly verify the circuit, VerilUOC_Desktop requires all inputs of the flip flops are connected to some value. So, it is necessary to connect "S" inputs to 0 and "load" inputs to 1. To do so, click in "Wiring" (left menu), select "Constant" and connect the constant (a logical 1) to the “load" inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs.

Example:

Instructions to answer this question

1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.

2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.

3) In "Module" select "Graded Exercises" and click on exercise 6.2.b

4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.

Answer: XZFC

Question 3)

Outputs of binary counters are square signals whose frequencies are sub-multiples of the main clock (\small{clk}clk) frequency. Based on this fact, counters are often used to generate clock signals of different frequencies. Let’s consider a 4-bits, binary up-counter with outputs \small{q3}q3, \small{q2}q2, \small{q1}q1 and \small{q0}q0 (\small{q3}q3 is the most significant bit). If the main clock signal (clk) has a frecuency of 2MHz, which will be the frequency of output signal \small{q1}q1?.

4 MHz
1 MHz
500 KHz
250 KHz

Question 4)

Design a 2-bit binary, cyclic up-counter and use it to implement a circuit that generates continuously the sequence 1001 and displays it by the output OUT (the leftmost bit of the sequence is generated when the counter is in the initial state 00). The counter increases by 1 at every positive edge of the clock signal.The final circuit will have the following inputs and outputs (use exactly these names for inputs and outputs):

clk: Input. Clock signal.

RST: Reset signal. When RST = 1 the counter is reset to 00.

OUT: Output.

Note 1: All flip flops must be synchronized by the "clk" signal (For experts: do not use "ripple-counter" or similar architectures)

Note 2: To properly verify the circuit, VerilUOC_Desktop requires all inputs of the flip flops are connected to some value. So, it is necessary to connect "S" inputs to 0 and "load" inputs to 1. To do so, click in "Wiring" (left menu), select "Constant" and connect the constant (a logical 1) to the “load" inputs. Repeat the process and, in the Value property of the left menu, replace the 0x1 by 0x0 (this will set the constant to 0). Connect the resulting constant to the "S" inputs.

Instructions to answer this question

1) In the virtual machine, open VerilUOC_Desktop and draw the circuit.

2) Click in “Simulate”->”Verification” and then click in the VerilCirc tab.

3) In "Module" select "Graded Exercises" and click on exercise 6.4.a

4) VerilCirc returns a 4 uppercase letters code. Type it in the answer box.

Answer: BKEJ

Question 5)

Module COUNT is a 3-bit binary up-counter with parallel load. While “load”=0, counter increases by 1 each time a positive edge of clk occurs. If “load”= 1, entries are loaded into the counter at the next positive edge. Complete the time chart for the circuit in figure 1.

Note that the circuit generates a cyclic output sequence y1, y0 = (0, 1, 3, 3, 2) by using a 3-bit counter with “synchronous reset” (“synchronous reset” means that counter is set to 0 when “load”=1 and a positive clock edge occurs)